Hybrid automatic repeat request (Hybrid ARQ or HARQ) is a combination of high-rate forward error-correcting coding, and ARQ error-control for detectable-but-uncorrectable errors. In standard ARQ, redundant bits are added to data to be transmitted using an error-detecting code such as cyclic redundancy check (CRC). In Hybrid ARQ, a code is used that can perform both forward error correction (FEC) in addition to error detection (ED) (such as Reed-Solomon code, Convolutional code or Turbo code), to correct a subset of all errors while relying on ARQ to correct errors that are uncorrectable using only the redundancy sent in the initial transmission. As a result Hybrid ARQ performs better than ordinary ARQ in poor signal conditions, but in its simplest form this comes at the expense of significantly lower throughput in good signal conditions. There is typically a signal quality cross-over point below which simple Hybrid ARQ is better, and above which basic ARQ is better.
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The simplest version of HARQ, Type I HARQ, adds both ED and FEC information to each message prior to transmission. When the coded data block is received, the receiver first decodes the error-correction code. If the channel quality is good enough, all transmission errors should be correctable, and the receiver can obtain the correct data block. If the channel quality is bad, and not all transmission errors can be corrected, the receiver will detect this situation using the error-detection code, then the received coded data block is rejected and a retransmission is requested by the receiver, similar to ARQ (Comroe/Costello 1984, pp. 474).
In a more sophisticated form, Type II HARQ, the message originator alternates between message bits along with error detecting parity bits and only FEC parity bits. When the first transmission is received error free, the FEC parity bits are never sent. Also, two consecutive transmissions can be combined for error correction if neither is error free (Comroe/Costello 1984, pp. 474-5).
To understand the difference between Type I and Type II Hybrid ARQ, consider the size of ED and FEC added information: error detection typically only adds a couple of bytes to a message, which is only an incremental increase in length. FEC, on the other hand, can often double or triple the message length with error correction parities. In terms of throughput, standard ARQ typically expends a few percent of channel capacity for reliable protection against error, while FEC ordinarily expends half or more of all channel capacity for channel improvement.
In standard ARQ a transmission must be received error free on any given transmission for the error detection to pass. In Type II Hybrid ARQ, the first transmission contains only data and error detection (no different than standard ARQ). If received error free, it's done. If data is received in error, the second transmission will contain FEC parities and error detection. If received error free, it's done. If received in error, error correction can be attempted by combining the information received from both transmissions.
Only Type I Hybrid ARQ suffers capacity loss in strong signal conditions. Type II Hybrid ARQ does not, because FEC bits are only transmitted on subsequent retransmissions as needed. In strong signal conditions, Type II Hybrid ARQ performs with as good capacity as standard ARQ. In poor signal conditions, Type II Hybrid ARQ performs with as good sensitivity as standard FEC.
In practice, incorrectly received coded data blocks are often stored at the receiver rather than discarded, and when the retransmitted block is received, the two blocks are combined. This is called Hybrid ARQ with soft combining (Dahlman et al., p. 120). While it is possible that two given transmissions cannot be independently decoded without error, it may happen that the combination of the previously erroneously received transmissions gives us enough information to correctly decode. There are two main soft combining methods in HARQ:
Several variants of the two main methods exist. For example, in partial Chase combining only a subset of the bits in the original transmission are retransmitted. In partial incremental redundancy, the systematic bits are always included so that each retransmission is self-decodable.
An example of incremental redundancy HARQ is HSDPA: the data block is first coded with a punctured 1/3 Turbo code, then during each (re)transmission the coded block is usually punctured further (i.e. only a fraction of the coded bits are chosen) and sent. The puncturing pattern used during each (re)transmission is different, so different coded bits are sent at each time. Although the HSDPA standard supports both chase combining and incremental redundancy, it has been shown that incremental redundancy almost always performs better than chase combining, at the cost of increased complexity[1].
HARQ can be used in stop-and-wait mode or in selective repeat mode. Stop-and-wait is simpler, but waiting for the receiver's acknowledgment reduces efficiency. Thus multiple stop-and-wait HARQ processes are often done in parallel in practice: when one HARQ process is waiting for an acknowledgment, another process can use the channel to send some more data.
There are other forward error correction codes that can be used in an HARQ scheme besides Turbo codes, e.g. extended irregular repeat-accumulate (eIRA) code and Efficiently-Encodable Rate-Compatible (E2RC) code, both of which are Low Density Parity Check Code.
HARQ is used in HSDPA and HSUPA which provide high speed data transmission (on downlink and uplink respectively) for mobile phone networks such as UMTS, and in the IEEE 802.16-2005 standard for mobile broadband wireless access, also known as "mobile WiMAX". It also has been used in 3GPP Long Term Evolution (LTE).
Type I Hybrid ARQ is also used in ITU-T G.hn, a high-speed Local area network standard that can operate at data rates up to 1 Gbit/s over existing home wiring (power lines, phone lines and coaxial cables). G.hn uses CRC-32C for Error Detection, LDPC for Forward Error Correction and Selective Repeat for ARQ.
HARQ is generally implemented in hardware, rather than in software.